Thin film transistors can be divided into bottom-gated thin film transistors and top-gated thin film transistors according to structure of the thin film transistors. In this way, parasitic capacitance, formed between a source/drain and a gate of the top-gated thin film transistor, may be significantly reduced, thereby increasing open-state current of the thin film transistor and enhancing operational speed of a device with the transistor, which facilitates reduced size of the device. Thus, it has become a hot industrial research area in recent years.
In conventional methods for manufacturing top-gated thin film transistors, steps of forming a gate pattern specifically include forming a gate metal layer, and performing an etching process on the gate metal layer. However, in the process of etching the gate metal layer, the metal can easily be over-etched, such that a width of the gate pattern is smaller than a width of a channel region of a conductive channel, and the gate cannot completely control the conductive channel. Thus, current between the source and the drain is reduced, and performance of the device with thin film transistors is reduced.
Therefore, it is necessary to provide a method for manufacturing top-gated thin film transistors to solve the problems which exist in the prior art.